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How to Find Input Capacitance Using Spice --Kostas Pagiamtzis, Ph.D.
http://www.pagiamtzis.com/articles/how-to-find-input-capacitance-using-spice/
How to Find Input Capacitance Using Spice
Spice is the circuit designer's Swiss Army knife. We use it whenever we need to precisely determine the properties of our circuits. This page shows how to find the input capacitance of a node (usually the input of a digital circuit, like an inverter) using Spice.
You build a CMOS inverter for your boss and she asks you what the input capacitance is. You answer: “I'm not sure, but I will find out right away!” What you should have been able to say to her is: “Well, boss, the first thing I did was to familiarize myself with the 12nm CMOS process and I found that the input capacitance is 0.8 fF/μm, so of course my 7μm PMOS, 3μm NMOS inverter has about 8 fF of input capacitance. ” But you didn't say that, because you didn't know. You are a spice monkey.
Don't be so dependent on Spice. You should always be able to predict an approximate answer to simple questions like this without resorting to a Spice simulation. The typical things you should know about the transistor process you are designing in: gate capacitance per unit width of transistor gate (for minimum length), diffusion capacitance per unit area, effective resistance (when used in a digital gate) in Ωμm, and fanout-of-4 (FO-4) delay. Of course, you need a way to find all these parameters and even though approximations these parameters are very useful for choosing topologies and calculating results to a first order, eventually you need more precise quantities. For those cases, Spice is the right tool.
To paraphrase Sun Tzu in The Art of War:
If you know Spice and yourself, you need not fear the result of a hundred simulations. If you know yourself but not Spice, for every successful simulation you will also suffer a defeat. If you know neither Spice nor yourself, you will succumb in every simulation.
One way to find capacitance using Spice is to build two copies of your circuit. One copy is loaded by the capacitive device that you are trying to characterize and the other copy is loaded by a simple capacitance (a C element in Spice) with the amount of capacitance set as a parameter. You then sweep through a series of values for the C, finding the value that causes the circuits to match. The way they match is up to you. Common methods of matching circuits is in terms of rise delay, fall delay, rise time (10% to 90%) or fall time (90% to 10%).
The Spice deck below shows an example of sweeping the capacitance CLOAD to find the input capacitance of the inverter Xinv0_load. We find its capacitance by finding the value of CLOAD that causes the two circuits to have the same average delay—measured from the 50% crossing point of the input waveform to the 50% crossing point of the output waveform and averaged for a rising and falling edge. Once we know this value of CLOAD, we know it is equivalent to the input capacitance of Xinv0_load for the purpose of finding rise/fall time.
The basic structure of the Spice deck below is to instantiate the appropriate power supplies, input signal waveform, the first circuit consisting of inverters Xinv0_driver and Xinv0_load , and the second circuit consisting of Xinv1_drive (the same as Xinv0_driver) and the capacitance parameterized with CLOAD.
The sweep notation in the .tran analysis statement runs multiple simulations with a range of values for the parameter CLOAD.
* Find the input capacitance using sweep method .lib 'my-transistor.lib' TT .temp 25 .param vd=1V * Power supplies Vvdd vdd 0 dc vd Vvss vss 0 dc 0 * Input waveform Vin in 0 PULSE 0 vd 100ps 80ps 80ps 500ps 1u * First circuit, uses the load we are trying to characterize Xinv0_driver mid0 in vdd vss inv WP=2 WN=1 Xinv0_load out0 mid0 vdd vss inv WP=10 WN=5 * Second circuit, uses a parameterized load capacitor Xinv1_driver mid1 in vdd vss inv WP=2 WN=1 Cload mid1 vss CLOAD * Measure rising and falling edge (with respect to the output edge) time delays for * the real copy of the circuit. .measure TRAN tdr TRIG v(in) VAL='0.5*vd' FALL=1 TARG v(mid0) VAL='0.5*vd' RISE=1 .measure TRAN tdf TRIG v(in) VAL='0.5*vd' RISE=1 TARG v(mid0) VAL='0.5*vd' FALL=1 .measure TRAN tdavg PARAM='(tdr+tdf)/2' * Measure the same parameters for the model circuit loaded by CLOAD .measure TRAN tdrc TRIG v(in) VAL='0.5*vd' FALL=1 TARG v(mid1) VAL='0.5*vd' RISE=1 .measure TRAN tdfc TRIG v(in) VAL='0.5*vd' RISE=1 TARG v(mid1) VAL='0.5*vd' FALL=1 .measure TRAN tdavgc PARAM='(tdrc+tdfc)/2' .tran 1ps 1ns SWEEP data = info .data info CLOAD 10fF 11fF 12fF 13fF 14fF 15fF 16fF 17fF 18fF 19fF 20fF .enddata .subckt inv out in pow gnd WP=2u WN=1u mn out in gnd gnd W=WN L=LMIN * assume LMIN is defined in library mp out in pow pow W=WP L=LMIN * assume LMIN is defined in library .ends .probe v(*) .end
Notice that the sweep in this deck will steps in increments of 1fF. So if you need a more precise value, either run more steps in the sweep, or do a second sweep, once the first sweep has bracketed the capacitance with within one fF.
Since the real input capacitance of Xinv0_load is nonlinear, even a highly precise sweep of CLOAD is an approximation, albeit one that is quite accurate. You can find the equivalent CLOAD to mach some other parameter between the circuits, such as average 10%-to-90% rise/fall time. You will find that the resulting CLOAD will be somewhat different from the one that matches the circuits based on the average %50-to-%50 delay. It's best to match the circuits using the parameter(s) that you will later use CLOAD to find. So if you will be using CLOAD to predict dynamic power consumption, then it's a good idea to match the two circuits based on power consumption.
There is another, more elegant way to find CLOAD using the built-in optimizer of Hspice, one of the commercial versions of Spice. If you use another flavor of Spice, or a variant like Spectre, there is probably an equivalent way of performing optimization, although the syntax may be slightly different.
The Hspice deck for find the matching CLOAD is presented below. The deck is largely the same as the sweep method above, with a few important changes. One change is the way the parameter CLOAD is initialized. We use the syntax OPTC(15FF, 1fF, 30fF), telling the iterative optimizer to start with 15fF as the initial CLOAD value and to freely range between 1fF and 30fF to find the solution. The second change is the addition of the GOAL=tdavg parameter to the .measure statement that defines tdavgc. This tells tells the optimizer that the it should strive to choose CLOAD such that tdavgc is equal to tdavg. The .tran statement is updated to indicate that this is an optimization analysis and it describes which measure statement to optimize (tdavgc in this case). Finally, we also add the line .model OPT1 opt to signal to Hspice that this is an optimization deck.
* Find the input capacitance using Hspice optimizer .lib 'my-transistor.lib' TT .temp 25 .param vd=1V .param CLOAD=OPTC(15fF, 1fF, 30fF) * Power supplies Vvdd vdd 0 dc vd Vvss vss 0 dc 0 * Input waveform Vin in 0 PULSE 0 vd 100ps 80ps 80ps 500ps 1u * First circuit, uses the load we are trying to characterize Xinv0_driver mid0 in vdd vss inv WP=2 WN=1 Xinv0_load out0 mid0 vdd vss inv WP=10 WN=5 * Second circuit, uses a parameterized load capacitor Xinv1_driver mid1 in vdd vss inv WP=2 WN=1 Cload mid1 vss CLOAD * Measure rising and falling edge (with respect to the output edge) time delays for * the real copy of the circuit. .measure TRAN tdr TRIG v(in) VAL='0.5*vd' FALL=1 TARG v(mid0) VAL='0.5*vd' RISE=1 .measure TRAN tdf TRIG v(in) VAL='0.5*vd' RISE=1 TARG v(mid0) VAL='0.5*vd' FALL=1 .measure TRAN tdavg PARAM='(tdr+tdf)/2' * Measure the same parameters for the model circuit loaded by CLOAD .measure TRAN tdrc TRIG v(in) VAL='0.5*vd' FALL=1 TARG v(mid1) VAL='0.5*vd' RISE=1 .measure TRAN tdfc TRIG v(in) VAL='0.5*vd' RISE=1 TARG v(mid1) VAL='0.5*vd' FALL=1 .measure TRAN tdavgc PARAM='(tdrc+tdfc)/2' GOAL=tdavg * We set the GOAL to tdavg which will cause the optimizer to try * select a CLOAD that cause tdavgc to match tdavg .model OPT1 opt .tran 1ps 1ns SWEEP OPTIMIZE=optc RESULTS=tdavgc MODEL=OPT1 .subckt inv out in pow gnd WP=2u WN=1u mn out in gnd gnd W=WN L=LMIN * assume LMIN is defined in library mp out in pow pow W=WP L=LMIN * assume LMIN is defined in library .ends .probe v(*) .end
This deck is elegant in that there no need to do multiple sweeps. Hspice will find the result to a useful precision. One caveat is that the general view amongst most circuit designers I know is that the Hspice optimizer is a piece of crap. It works just fine for simple optimizations like the one above, but can fail to converge or, even worse, give the wrong answer for optimizations of many variables. This deck is simple enough, that I have never encountered a problem using it with the Hspice optimizer. To help Hspice converge to a solution as quickly as possible, it is a good idea to give a reasonable starting point and range for all optimization parameters.
The first time you have to perform a task like finding input capacitance it's worth taking the time to build a good Spice deck, whether you use the sweep method or optimization method or find your own more clever method. You will find that as you have to repeat these tasks, all you will have to do is brush off an old Spice deck, make some minor modifications and you'll be quickly done. Then you can spend your time doing real thinking and less simulating.
dlmread and dlmwrite
Just found two useful functions in Matlab. It is easy to read and write ascii data file with them.
使用“GetData Graph Digitizer”从图像文件中提取X-Y数值点
使用合:1、想引用别人论文中的某个数据(曲线)图,但论文中没有这个图的数据,直接把图抓过来显得太逊了,希望提取出这个图中的数据信息生成矢量图;2、希望从这个图中提取出数据用于自己的研究;
软件来源:此软件由俄国人开发(好多这种功能强大的小软件都是俄国人开发的,pfpf)getdata-graph-digitizer.com上可以下载到试用版,21天的试用期,好像无功能限制,目前最新版本:2.24,有中文和英文界面可供选择,其他有俄文、乌克兰文、日文、朝鲜文,居然还有印度尼西亚文(开发者有印尼朋友?);
使用方法:
1 启动GetData Graph Digitizer,打开要处理的图像文件;
2 设置背景颜色和曲线颜色(“操作->设定背景/线段颜色”),后续拾取数值点的操作要基于颜色信息;
3 设置坐标轴的位置和起始值范围(“操作->设定标尺刻度”);
4 “操作->数字化区域”,启动“数字化区域”方法提取数据点,曲线上提取点的密度由“操作->数字化区域->栅格设置”下dx的值控制(值越大越稀疏),设置好栅格后鼠标变为黑色箭头,用之拖出一个矩形区域,区域内部的曲线就会被自动提取了。这种方法的好处是可以非常简单的(一次操作)提取出所有的数据点,如果选上了不想要的点可以用“操作->数据点移除器”去除,如果点的顺序不对可以用“操作->重新排序工具”改为正确的顺序;
4.1 另一种“自动跟踪线段”方法需要多次手工选取曲线上的点,比较麻烦;
另:“设置->语言”中可以更改界面的语言;
Using CYGWIN and SSH to display Unix windows on MS Windows computers
e680i LOADER, MPKG, TELNET 及其他

绳结
日常许多事务都需使用结,从事各项活动时,选择正确合适的结极为重要。当需要打结时,不应该一无所知。要学习、掌握每种结的用途及如何打结--在黑暗之中和其他各种条件下要能自如打结;同时也应知道如何解开结--在许多危险时刻,不会开结比不会打结更糟糕。
说明:在以下叙述中,用来打结的绳索被提起的一端我们称之为活端;与此区分,绳索的另一端我们称之为固定部分或固定端。
简单的结:
有一些结十分简单,制作快速,掌握它们的制作方法,有助于对下文所述的更复杂的结加深了解。
※平结※
又称为方结,在各种类型的结中,平结使用频率最高,也最为人所熟知。用平结将粗细相同的绳索连在一起,即使承受拉力很大,也十分结实,而且易于解开。
粗细不同的绳索用此结系在一起并不可靠,使用尼龙绳时也不应打平结--尼龙绳太滑。
也可利用平结将绳索系在其他物体上。在营救中使用平结较好,它十分光滑,不易伤着遇难者。
a、将右边一根放在左边的绳子上面;
b、向下环绕,然后将左边绳端放;
c、在右边绳端上;
d、再向下环绕。
小心检查--两个环可以彼此滑动,如果穿错了位置,就会导致系不到一起(散开),或者在受到拉力时难以解开。
同时拉动两根绳索,将平结系紧;或者仅从活端用力,也能确保系紧e。
系完平结后如怀疑是否可靠,可将平结每一端的活端在绳索上再打半个索结f。
※反手结※
有所有的结当中,反手结最简单。首先将绳索曲成一环状,将活端从后面穿过此环拉紧即成。反手结除了用一在绳端处打一结点(使绳头不易散开)外,很少有其他用场,但它是许多其他结的组成部分。(图上)
※反手环(结)※
此结制作极为快速,首先将绳索弯成一环,将此环套在一固定物体上,紧拉,再用活端与环打一反手结。(图下)。
※“8”字形结※
此结同反手结一样可在绳端系一个结点,但却比反手结更为有效。先将绳弯曲成一环,将活端放至绳索固定部分的后面,然后绕过固定部分,再将活端穿过前面的环。
※“8”字形环※
此环比反手环更结实牢固,制作方法与“8”字形结相同,但使用双股线,将环端作为活端,可放在用来系绳索的钉锚上。
※“8”字结第二种编织法※
这是一种将绳索系在锚上的相当有效的结。可在物体(锚)过高不能将打好的结套上的时候使用。首先在绳索上制作一松弛的“8”字形结,将活端绕过物体再拉回,沿着原8字形结的线路重新作一“8”字形,然后系紧即可。
※单编结※
用来连接粗细相同或不同的两根绳索,这比两根粗细相同的绳索系成的平结更为有效。对于材料不同的绳索,特别是潮湿或结冰的绳索,此结较理想。
此结制作简单,在绳索未承受拉力时也容易解开。如果制作方法无误,且承受的拉力是稳定规则的,则此结不会滑开。
1、将一绳弯曲成环状,另一绳的活端a向右,从后面绕过环,再将活端从这根绳与另一绳之间的环间穿过。
2、拉紧。拉力增加时,此结自动系紧。
※双编结※
双编结比单编结更结实耐用,对潮湿的绳索效果不错,特别是在两根绳索间粗细相差悬殊时。不过,即使两根绳索都很粗,使用双编结连接也十分结实。如果绳索受到的拉力不稳定,普通的单编结就容易滑落,此时更能显出双编结的优点。
1、将粗一点的绳索弯曲成环状,将细绳的活端a穿过此环,先移到粗绳活端的下面,再从前面开始环绕此环一周,然后从后面将细绳活端穿过细绳与粗绳活端之间。
2、将细绳活端再次环绕一周,再穿过相同地方(细绳与粗绳活端之间)。
3、拉紧,此结完成。
如果未拉紧,此结受力时容易松动。制作此结不宜使用光滑的绳索,如尼龙质的钓鱼线。
※渔人结※
连接两根质地柔软的绳索(或其他材料)时可采用此结,例如藤本或金属线。对于潮湿的或打滑的绳线也很有效,特别适于连接捕鱼用的钓线--首先在水中浸泡钓线,使其柔软。用此结连接细线时紧密牢固,但不易解开,在不能肯定平结或单编结是否有效时,可试用此结。但粗绳索或尼龙线不可使用此结。
1、将两根线放在一起,末端方向相反,将其中一线的活端绕过另一根线,简单制作一反手结。
2、用同样方式,重复另一根线的活端。
3、轻微拉紧两个反手结,然后彼此相向滑动,让两结紧挨,再系紧两结。
※两层渔人结※
这是渔人结类型中更加牢固的一种形式,但尼龙线、尼龙绳及粗笨绳索不能使用此结。
1、将其中一根线的活端环绕另一根线一次,然后再绕一次。
2、将活端穿过已形成的两环。
3、用同样方式,重复另一根线的活端。
4、将两个结彼此相向滑至一处,小心移动系紧两结。
※带结※
对于表面平滑的材料如皮带、布带等的连接,此结效果不错。当情况紧急、缺少绳索时,甚至可用被单或其他织物试一试。
1、用一根带子活端制作一个反手结,不要拉紧。
2、将另一根带子的活端沿反手结的运动轨迹的相反方向穿越此结。
3、活端应该恰好在结内,这样,拉紧时活端就不会滑落。
※单套环※
此环制作快速承受拉力时,既不变紧也不滑动。可用于救生环的末端或其他需要绳环固定的场合。
1、在离绳端一定距离处弯曲一个小环。
2、将活端向上穿过此环,从绳索固定部分后部绕过,然后向下再穿过此环。
3、拉动活端,使其变紧,小心使结固定。
※活动单套环※
此环可以滑动,可以任意松紧。先制作一个小的单套
环,然后将绳子长端从此环穿过。
不能将活动单套环系于腰间,特别在登山时更应注意。此环的功能类似悬挂人的绞索,可以致命。
※三重单套环※
是单套环的另一种类型,由两股绳制作。先将绳弯曲成环,将双股绳的活端穿过此环,然后从固定部分后面绕过,向下再穿过此环,这样就可产生三重绳环。可用来拖运设备或作为悬挂带:一股绳环环绕大腿,其他绳环环绕胸部。
掌握好比例需要一段时间的练习--所以使用之前要掌握制作技巧。
※环中环※
可以用来支撑或拉出的冰隙裂缝中或其他难以爬出地方的人员。制作时,绳子需双股,制作好的两环既不过紧也不挤压。用一个环绕过臀部,另一环绕过上体,就似一个工作吊板。
1、将双股绳索弯曲成一环,将活端穿过此环。
2、将活端向下(a),然后套过双层环(b),轻轻移至固定部分后面(c),拉动大的双层环,使其变紧(d)。
像三重单套环一样,在使用前,要练习一番。你会发现环中环有许多用途,装潢房屋或船舶时,为支撑悬挂的平台,可在每一端使用此环。如平台每个角有木杆,可在木杆上刻出凹槽,防止绳索滑落
※攀踏结※
通常也被称为蝴蝶结或炮结。此结有一个不可滑动的环,能够在绳索中间制作,但是在绳索末端不能用此结。在一根绳索上能够打出数个攀踏结,将人体套上,可以拉动,也可以抬起。登山时,携带打有攀踏结的绳索相当便利,手脚都可放在环上支撑身体,在感到疲劳时,还可以在上面休息一会。
1、2、将绳子折成一环。
3、再扭曲出一个小环。
4、将小环穿过原环。
5、轻轻拉动使结固定,小心拉紧。
注意:如果在拉紧结时不小心出现错误,就可能成为一个滑环。
※套索※
这是另一种能够自由滑动的套索结,但此种结有一个明显的圆形环,适于投掷套取某物,所以是一种套索。套索的功能多种多样,但在野外求生时,如果仅有一根绳索,那么花费许多的时间和精力试图用这种方式捕获动物并不明智,因为这需要长时间的实践。在你真正需要绳索时,或许它已经因为捕猎而损坏。但是,花时间练习用此种方法捕猎是值得的--掌握技能后,在真正的困境下就会取得回报。
1、首先打一反手结。
2、在离绳端一段距离弯曲一个环。
3、在反手结与环之间再将绳索折成半环。
4、将半环穿过先曲成的绳环。
5、绕着半环将绳环系紧。
6、将绳索的长端穿过新的绳环。
在用套索捕猎时,应注意手中绳索的长度。一只体型大的动物肯定会逃跑,如果绳索未抓牢,就可能让动物拖走,那就会偷鸡不成反蚀米。而将绳索固定在身上又会被动物拖,弄不好会严重受伤。那么,可以利用固牢的“锚”承受动物的拉力吗?答案是肯定的,将绳索绕过树干或一块岩石或许就会安然无恙,否则拉力过猛时人体难以承受。